View CAT5171TBI-00GT3_5454690.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2009 august, 2009 ? rev. 1 1 publication order number: cat5171/d cat5171 256-position i 2 c compatible digital potentiometer the cat5171 is a 256 ? position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. the wiper settings are controlled through an i 2 c ? compatible digital interface. upon power ? up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. the device can be programmed to reset the wiper position to midscale or to go to a shutdown state during operation. an address input pin, ad0, allows the connection of two devices onto the same i 2 c bus. the cat5171 operates from 2.7 v to 5.5 v, while consuming less than 2 a. this low operating current, combined with a small package footprint, makes the cat5171 ideal for battery ? powered portable applications. the cat5171, designed as a pin for pin replacement for the ad5245, is offered in the 8 ? lead sot23 package and operates over the ? 40 c to +85 c industrial temperature range. features ? 256 ? position ? end ? to ? end resistance: 50 k , 100 k ? i 2 c compatible interface ? power ? on preset to midscale ? single supply 2.7 v to 5.5 v ? low temperature coefficient 100 ppm/ c ? low power, i dd 2 a max ? wide operating temperature ? 40 c to +85 c ? rohs ? compliant sot ? 23 8 ? lead (2.9 mm x 3 mm) package typical applications ? potentiometer replacement ? transducer adjustment of pressure, temperature, position, chemical, and optical sensors ? rf amplifier biasing ? gain control and offset adjustment http://onsemi.com pin connections sda ad0 b a scl gnd v dd w 1 (top view) see detailed ordering and shipping information in the package dimensions sect ion on page 2 of this data sheet. ordering information sot23 ? 8 tp, tb suffix case 527ak af = 50 k ag = 100 k y = production year y = (last digit) m = production month m = (1 ? 9, a, b, c) afym marking diagram 1 agym 1
cat5171 http://onsemi.com 2 power on midscale ad0 a b w sda gnd figure 1. functional block diagram v dd i 2 c interface and control scl table 1. ordering information part number resistance temperature range package shipping ? cat5171tbi ? 50gt3 50 k ? 40 c to 85 c sot ? 23 ? 8 (pb ? free) 3000/tape & reel cat5171tbi ? 00gt3 100 k 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. table 2. pin function description pin no. pin name description 1 w resistor?s wiper terminal 2 v dd positive power supply 3 gnd digital ground 4 scl serial clock input 5 sda serial data input 6 ad0 i 2 c address bit 0 input 7 b bottom terminal of resistive element 8 a top terminal of resistive element table 3. absolute maximum ratings (note 1) rating value unit v dd to gnd ? 0.3 to 6.5 v v a , v b , v w to gnd v dd i max 20 ma digital inputs and output voltage to gnd 0 to 6.5 v operating temperature range ? 40 to +85 c maximum junction temperature (t jmax ) 150 c storage temperature ? 65 to +150 c lead temperature (soldering, 10 sec) 300 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package , and maximum applied voltage across any two of the a, b, and w terminals at a given resistance.
cat5171 http://onsemi.com 3 table 4. electrical characteristics: 50 k and 100 k versions v dd = 2.7 v to 5.5 v; v a = v dd ; v b = 0 v; ?40 c < t a < +85 c; unless otherwise noted. parameter test conditions symbol min typ (note 2) max unit dc characteristics ? rheostat mode resistor differential nonlinearity (note 3) r wb , v a = no connection r ? dnl ? 1 0.1 +1 lsb resistor integral nonlinearity (note 3) r wb , v a = no connection r ? inl ? 2 0.4 +2 lsb nominal resistor tolerance (note 4) t a = 25 c r ab ? 20 +20 % resistance temperature coefficient v ab = v dd , wiper = no connection r ab / t 100 ppm/ c wiper resistance v dd = 5 v, i w = 3 ma r w 50 120 v dd = 3 v, i w = 3 ma 100 250 dc characteristics ? potentiometer divider mode resolution n 8 bits differential nonlinearity (note 5) dnl ? 1 0.1 +1 lsb integral nonlinearity (note 5) inl ? 1 0.4 +1 lsb voltage divider temperature coefficient code = 0x80 v w / t 100 ppm/ c full ? scale error code = 0xff v wfse ? 3 ? 1 0 lsb zero ? scale error code = 0x00 v wzse 0 1 3 lsb resistor terminals voltage range (note 6) v a,b,w gnd v dd v capacitance (note 7) a, b f = 1 mhz, measured to gnd, code = 0 x 80 c a,b 45 pf capacitance (note 7) w f = 1 mhz, measured to gnd, code = 0 x 80 c w 60 pf common ? mode leakage (note 7) v a = v b = v dd /2 i cm 1 na digital inputs input logic high v dd = 5 v v ih 0.7 x v dd v input logic low v dd = 5 v v il 0.3v dd v input logic high v dd = 3 v v ih 0.7 x v dd v input logic low v dd = 3 v v il 0.3v dd v input current v in = 0 v or 5 v i il 1 a power supplies power supply range v dd range 2.7 5.5 v supply current v ih = 5 v or v il = 0 v i dd 0.3 2 a power dissipation (note 7) v ih = 5 v or v il = 0 v, v dd = 5 v p diss 0.2 mw power supply sensitivity v dd = +5 v 10%, code = midscale pss 0.05 %/% dynamic characteristics (notes 7 and 9) bandwidth ?3 db r ab = 50 k / 100 k , code = 0x80 bw 100/40 khz total harmonic distortion v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k thd w 0.05 % v w settling time (50 k /100 k ) v a = 5 v, v b = 0 v, 1 lsb error band t s 2 s 2. typical specifications represent average readings at +25 c and v dd = 5 v. 3. resistor position nonlinearity error r ? inl is the deviation from an ideal value measured between the maximum resistance and the minim- um resistance wiper positions. r ? dnl measures the relative step change from ideal between successive tap positions. parts are guaran- teed monotonic. 4. v ab = v dd , wiper (v w ) = no connect. 5. inl and dnl are measured at vw with the digital potentiometer configured as a potentiometer divider similar to a voltage outp ut d/a con- verter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6. resistor terminals a, b, w have no limitations on polarity with respect to each other. 7. guaranteed by design and not subject to production test. 8. maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 9. all dynamic characteristics use v dd = 5 v.
cat5171 http://onsemi.com 4 table 5. capacitance t a = 25 c, f = 1.0 mhz, v dd = 5 v symbol test conditions max units c i/o (note 10) input/output capacitance (sda, scl) v i/o = 0v 8 pf table 6. power up timing (notes 10 and 11) symbol parameter max units t pur power ? up to read operation 1 ms t puw power ? up to write operation 1 ms 10. this parameter is tested initially and after a design or process change that affects the parameter. 11. t pur and t puw are delays required from the time v cc is stable until the specified operation can be initiated. table 7. digital potentiometer timing symbol parameter min max units t wrpo wiper response time after power supply stable 50 s t wr wiper response time: scl falling edge after last bit of wiper position data byte to wiper change 20 s table 8. a.c. characteristics v dd = +2.7 v to +5.5 v, ? 40 c to +85 c unless otherwise specified. symbol parameter min typ max units f scl clock frequency 400 khz t high clock high period 600 ns t low clock low period 1300 ns t su:sta start condition setup time (for a repeated start condition) 600 ns t hd:sta start condition hold time 600 ns t su:dat data in setup time 100 ns t hd:dat data in hold time 0 ns t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1300 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t dh data out hold time 100 ns t i noise suppression time constant at scl, sda inputs 50 ns t aa scl low to sda data out and ack out 1 s
cat5171 http://onsemi.com 5 typical characteristics v dd = 2.6 v 3.3 v 5.6 v 4.0 v figure 2. differential non ? linearity, v dd = 5.6 v figure 3. integral non ? linearity, v dd = 5.6 v tap tap 256 224 160 128 96 64 32 0 ? 0.05 ? 0.04 ? 0.03 ? 0.02 ? 0.01 0.01 0.02 0.03 224 192 160 128 96 64 32 0 ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 figure 4. wiper resistance at room temperature figure 5. wiper voltage tap tap 250 200 150 100 50 0 0 20 40 60 80 100 120 260 208 156 104 52 0 0 1 2 3 4 5 6 error (lsb) error (lsb) rw ( ) vw (v) 0 192 dnl inl 256 v dd = 2.6 v 3.3 v 5.6 v 4.0 v 5.0 v figure 6. standby current v dd (v) 6 5 4 3 2 100 150 200 250 300 350 400 isb (na) t = ? 45 c t = 25 c t = 90 c
cat5171 http://onsemi.com 6 typical characteristics f (khz) f (khz) 1000 100 10 1 ? 36 ? 30 ? 24 ? 18 ? 12 ? 6 0 1000 100 10 1 0 5 10 15 20 25 30 a (db) psrr (db) v dd = 5 v v dd = 3 v v dd = 5 v v dd = 3 v figure 7. change in end ? to ? end resistance figure 8. end ? to ? end resistance vs. temperature temperature ( c) temperature ( c) 100 70 40 10 ? 20 ? 50 ? 0.2 0 0.2 0.4 100 70 40 10 ? 20 ? 50 101.75 101.80 101.85 101.90 101.95 102.00 102.05 102.15 (%) r (k ) 102.10 figure 9. gain vs. bandwidth (tap 0x80) figure 10. psrr
cat5171 http://onsemi.com 7 basic operation the cat5171 is a 256 ? position digitally controlled potentiometer. when power is first applied, the wiper assumes a mid ? scale position. once the power supply is stable, the wiper may be repositioned via the i 2 c compatible interface. programming: variable resistor rheostat mode the resistance between terminals a and b, r ab , has a nominal value of 50 k or 100 k and has 256 contact points accessed by the wiper terminal, plus the b terminal contact. data in the 8 ? bit w iper register is decoded to select one of these 256 possible settings. the wiper?s first connection is at the b terminal, corresponding to control position 0x00. ideally this would present a 0 between the wiper and b, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the r on of the fet switch connecting the wiper output with its respective contact point. in cat5171 this ?contact? resistance is typically 50 . thus a connection setting of 0x00 yields a minimum resistance of 50 between terminals w and b. for a 100 k device, the second connection, or the first tap point, corresponds to 441 (r wb = r ab /256 + r w = 390.6 + 50 ) for data 0x01. the third connection is the next tap point, is 831 (2 x 390.6 + 50 ) for data 0x02, and so on. figure 11 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. figure 11. cat5171 equivalent dpp circuit r s wiper register and decoder a w b r s r s r s the equation for determining the digitally programmed output resistance between w and b is r wb d 256 r ab r w (eq. 1) where d is the decimal equivalent of the binary code loaded in the 8 ? bit wiper register, r ab is the end ? to ? end resistance, and r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 100 k and the a terminal is open circuited, the following output resistance r wb will be set for the indicated wiper register codes: table 9. codes and corresponding r wb resistance for r ab = 100 k , v dd = 5 v d (dec.) r wb ( ) output state 255 99,559 full scale (r ab ? 1 lsb + r w ) 128 50,050 midscale 1 441 1 lsb 0 50 zero scale (wiper contact resistance) be aware that in the zero ? scale position, the wiper resistance of 50 is still present. current flow between w and b in this condition should be limited to a maximum pulsed current of no more than 20 ma. failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. similar to the mechanical potentiometer, the resistance of the dpp (digitally programmed potentiometer) between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is r wa (d) 256 d 256 r ab r w (eq. 2) for r ab = 100 k and the b terminal open circuited, the following output resistance r wa will be set for the indicated wiper register codes. table 10. codes and corresponding r wa resistance for r ab = 100 k , v dd = 5 v d (dec.) r wa ( ) output state 255 441 full scale 128 50,050 midscale 1 99,659 1 lsb 0 100,050 zero scale typical device to device resistance matching is lot dependent and may vary by up to 20%.
cat5171 http://onsemi.com 8 esd protection gnd logic digital input gnd potentiometer figure 12. esd protection networks w, a, b terminal voltage operating range the cat5171 v dd and gnd power supply define the limits for proper 3 ? terminal digital potentiometer operation. signals or potentials applied to terminals a, b or the wiper must remain inside the span of v dd and gnd. signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. w, a, b cat5171 logic gnd figure 13. v dd power ? up sequence because esd protection diodes limit the voltage compliance at terminals a, b, and w (see figure 12), it is recommended that v dd /gnd be powered before applying any voltage to terminals a, b, and w. the ideal power ? up sequence is: gnd, v dd , digital inputs, and then v a/b/w . the order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd /gnd. power supply bypassing good design practice employs compact, minimum lead length layout design. leads should be as direct as possible. it is also recommended to bypass the power supplies with quality low esr ceramic chip capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. as a further precaution digital ground should be joined remotely to the analog grou nd at one point to minimize the ground bounce. cat5171 gnd + 10 f 0.1 f figure 14. power supply bypassing v dd v dd c 3 c 1
cat5171 http://onsemi.com 9 i 2 c bus protocol the following defines the features of the i 2 c bus protocol: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5171 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5171 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the six most significant bits of the 8 ? bit slave address are fixed as 010110 for the cat5171. the next bit (ad0) is the device least significant address bit and defines which device the master is accessing. up to two devices may be individually addressed by the system. typically, +5 v (v dd ) or ground is hard ? wired to the ad0 pin to establish the device?s address. after the master sends a start condition and the slave address byte, the cat5171 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat5171 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 ? bit byte. when the cat5171 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5171 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operation in the write mode, the master device sends the start condition and the slave address information to the slave device. after the slave generates an acknowledge, the master sends the instruction byte. after receiving another acknowledge from the slave, the master device transmits the data to be written into the wiper register. the cat5171 acknowledges once more and the master generates the stop condition. figure 15. bus timing diagram t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat5171 http://onsemi.com 10 start condition sda stop condition scl figure 16. start/stop condition acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 17. acknowledge condition
cat5171 http://onsemi.com 11 instruction and register description slave address byte the first byte sent to the cat5171 from the master/processor is called the slave address byte. the most significant six bits of the slave address are a device type identifier. for the cat5171, these bits are fixed at 010110. the next bit, ad0, is the first bit of the internal slave address and must match the physical device address which is defined by the state of the ad0 input pin for the ca t5171 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the ad0 input can be actively driven by cmos input signals or tied to the supply voltage or ground. the next bit, r/w , indicates whether this command corresponds to a write or read instruction. to write into the wiper control register, r/w bit is set to a logic low; while a read from the wiper register is done with the bit high. wiper control the cat5171 contains one 8 ? bit wiper control register (wcr). the wiper control register output is decoded to select one of 256 switches along its resistor array. the contents of the wcr may be written by the host via write instruction. the wiper control register is a volatile register that loses its contents when the cat5171 is powered ? down. upon power ? up, the wiper is set to midscale and may be repositioned anytime after the power has become stable. instructions write and read instructions are respectively three and two bytes in length. the basic sequence of the two instructions is illustrated in table 11 and 12. in write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is a don?t care. the second msb, rs, is the midscale reset. a logic high on this bit moves the wiper to the center tap. the third msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a, and short the wiper terminal w to terminal b. the ?shutdown? operation does not change the contents of the wiper register. when the shutdown bit, sd, goes back to a logic low, the previous wiper position is restored. also during shutdown, new settings can be programmed. as soon as the device is returned from shutdown, the wiper position is set according to the wiper register value. two cat5171 on a single bus when needed, it is possible to connect two cat5171 potentiometers on the same i 2 c bus and be able to address each one independently. each device can be set to a unique address by using the ad0 input pin. one device ad0 pin is connected to ground, and the other d evice ad0 pin is tied to the supply voltage. table 11. write s 0 1 0 1 1 0 ad0 w a x rs sd x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte s t a r t 0 1 0 1 1 0 ad0 a c k xxxxx a c k sda s t o p a c k d7 slave address byte instruction byte data byte rs sd x d6 d5 d4 d3 d2 d1 d0 r/w table 12. read s 0 1 0 1 1 0 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte s t a r t 0 1 0 1 1 0 ad0 a c k sda s t o p n c k d7 slave address byte data byte d6 d5 d4 d3 d2 d1 d0 r/w a legend s = start p = stop a = acknowledge ad0 = address bit 0, needed when using two potentiometers on the same i 2 c bus. d = data bit r = read (bit is 1 for read instruction) w = write (bit is 0 for write instruction) rs = when the bit is 1, the wiper position is moved to mid ? scale 0x80 sd = shut down: 0: normal operation 1: wiper is parked at b terminal and terminal a is open circuit. x = don?t care
cat5171 http://onsemi.com 12 package dimensions sot ? 23, 8 lead case 527ak ? 01 issue a notes: (1) all dimensions in millimeters. angles in degrees. (2) complies with jedec standard mo-178. symbol e e1 a2 a3 a1 eb d c a top view side view end view l1 l2 l pin #1 identification min nom max a a1 a2 b c d e e1 l l2 0.00 0.90 0.28 0.08 2.90 bsc 1.60 bsc 0.45 1.45 0.15 1.30 0.38 0.22 0.25 ref 1.10 2.80 bsc l1 0.60 ref e 0.30 0.60 0.65 bsc 0.90 0 8 a3 0.60 0.80 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat5171/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of CAT5171TBI-00GT3

	To Download CAT5171TBI-00GT3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .